授课教师：Gilles Jacquemod

国籍：法国

职称：教授

教师简介（中英文）：

吉尔·雅克莫教授是法国蔚蓝海岸大学的全职教授，也是Polytech’Lab的负责人，他在微电子学领域享有广泛的声誉。他的学术生涯始于ICPI里昂工程师，继而在INSA里昂获得了集成电子学博士学位。他的成就包括发布超过400篇的出版物，并荣获法国高等教育和研究部颁发的'国家荣誉勋位'等多项荣誉。他的研究领域涵盖了物联网行为建模，低功耗消耗，射频和模拟电路设计，微控制器的电磁兼容性，以及人工智能。此外，他还在尼斯索菲亚综合理工的电子学部任教，并自2014年起，在中国的天津大学担任访问教授。

Professor Gilles Jacquemod, a Full Professor at University Côte d’Azur and head of Polytech’Lab, is renowned in the realm of microelectronics. His journey started as an engineer from ICPI Lyon, leading to a Ph.D. in Integrated Electronics from INSA Lyon. Adding more than 400 publications to his credit, he has received numerous accolades, including the 'Chevalier de l’Ordre National du Mérite' by the French Minister of Higher Education and Research. His research spans behavioral modeling for IoT, low-power consumption, RF and analog circuits design, electromagnetic compatibility on microcontrollers, and AI. Alongside, he is a dedicated teacher at the electronics department of Polytech Nice Sophia and a visiting professor at Tianjin University, China since 2014.

课程简介（中英文）：

本课程的目的是让学生全面了解微纳米电子行业的演变。课程从第一个基于双极晶体管的集成电路开始，重点是了解CMOS技术。

因此给出双极晶体管的主要特性，以及MOS晶体管(Spice模型)的主要特性。根据英特尔微处理器随着晶体管数量的增加而展示摩尔定律的演变，以及说明集成电路的复杂性如何随晶体管尺寸的减小而变化.我们将使用软件工具或EDA(电子设计自动化)来展示这种复杂的过程。最后，根据可变性和收缩效应、摩尔定律的极限以及FinFET或FDSOI晶体管，如何使工艺达到22纳米以下，来凸显CMOS技术的局限性。

"The purpose of this course is to provide students with a comprehensive understanding of the evolution of the micro- and nanoelectronics industry. The course starts with the first integrated circuits based on bipolar transistors and focuses on understanding CMOS technology.

Therefore, the main characteristics of bipolar transistors are given, as well as the main characteristics of MOS transistors (Spice model). Demonstrate the evolution of Moore's Law as the number of transistors increases based on Intel microprocessors and illustrate how the complexity of integrated circuits changes as transistor size decreases. We will use software tools or EDA (Electronic Design Automation) to demonstrate this a complex process. Finally, the limitations of COS technology are highlighted in terms of variability and shrinkage effects, the limits of Moore's Law, and FinFET or FDSOI transistors, how to get the process to sub-22nm. "